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74VCX32374 Low Voltage 32-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
December 2000 Revised November 2002
74VCX32374 Low Voltage 32-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
General Description
The VCX32374 contains thirty-two non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and output enable (OE) are common to each byte and can be shorted together for full 32-bit operation. The 74VCX32374 is designed for low voltage (1.2V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74VCX32374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
s 1.2V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD 3.0 ns max for 3.0V to 3.6V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal (Note 1) s Static Drive (IOH/IOL)
24 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance: Human body model > 2000V Machine model > 200V s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74VCX32374G (Note 2)(Note 3) Package Number BGA96A Package Descriptions 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 2: Ordering code "G" indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
(c) 2002 Fairchild Semiconductor Corporation
DS500402
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74VCX32374
Connection Diagram
Pin Descriptions
Pin Names OEn CPn I0-I31 O0-O31 Description Output Enable Input (Active LOW) Clock Pulse Input Inputs Outputs
FBGA Pin Assignments
1 A B C D E F G H (Top Thru View) J K L M N P R T O1 O3 O5 O7 O9 O11 O13 O14 O17 O19 O21 O23 O25 O27 O29 O30 2 O0 O2 O4 O6 O8 O10 O12 O15 O16 O18 O20 O22 O24 O26 O28 O31 3 OE1 GND VCC GND GND VCC GND OE2 OE3 GND VCC GND GND VCC GND OE4 4 CP1 GND VCC GND GND VCC GND CP2 CP3 GND VCC GND GND VCC GND CP4 5 I0 I2 I4 I6 I8 I10 I12 I15 I16 I18 I20 I22 I24 I26 I28 I31 6 I1 I3 I5 I7 I9 I11 I13 I14 I17 I19 I21 I23 I25 I27 I29 I30
Truth Tables
Inputs CP1 Outputs I0-I7 H L X X O0-O7 H L O0 Z CP2 Inputs Outputs I8-I15 H L X X O8-O15 H L O0 Z

L X
OE1 L L L H

L X
OE2 L L L H
Inputs CP3
Outputs I16-I23 H L X X O16-O23 H L O0 Z CP4
Inputs
Outputs I24-I31 H L X X O24-O31 H L O0 Z

L X
OE3 L L L H

L X
OE4 L L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of CP
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74VCX32374
Functional Description
The 74VCX32374 consists of thirty-two edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 32-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops.
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Byte 3 (16:23)
Byte 4 (24:31)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74VCX32374
Absolute Maximum Ratings(Note 4)
Supply Voltage (VCC ) DC Input Voltage (VI) Output Voltage (VO) Outputs 3-STATED Outputs Active (Note 5) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V VO > VCC DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG)
-0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V -0.5V to VCC +0.5V -50 mA -50 mA +50 mA 50 mA 100 mA -65C to +150C
Recommended Operating Conditions (Note 6)
Power Supply Operating Input Voltage Output Voltage (VO) Output in Active States Output in 3-STATE Output Current in IOH/IOL VCC = 3.0V to 3.6V VCC = 2.3V to 2.7V VCC = 1.65V to 2.3V VCC = 1.4V to 1.6V VCC = 1.2V Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Floating or unused inputs must be held HIGH or LOW.
1.2V to 3.6V
-0.3V to +3.6V
0V to VCC 0.0V to 3.6V
24 mA 18 mA 6 mA 2 mA 100 A -40C to +85C
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 2.7 - 3.6 2.3 - 2.7 1.65 - 2.3 1.4 - 1.6 1.2 VIL LOW Level Input Voltage 2.7 - 3.6 2.3 - 2.7 1.65 - 2.3 1.4 - 1.6 1.2 VOH HIGH Level Output Voltage IOH = -100 A IOH = -12 mA IOH = -18 mA IOH = -24 mA IOH = -100 A IOH = -6 mA IOH = -12 mA IOH = -18 mA IOH = -100 A IOH = -6 mA IOH = -100 A IOH = -2 mA IOH = -100 A 2.7 - 3.6 2.7 3.0 3.0 2.3 - 2.7 2.3 2.3 2.3 1.65 - 2.3 1.65 1.4 - 1.6 1.4 1.2 VCC - 0.2 2.2 2.4 2.2 VCC - 0.2 2.0 1.8 1.7 VCC - 0.2 1.25 VCC - 0.2 1.05 VCC - 0.2 V 2.0 1.6 0.65 x VCC 0.65 x VCC 0.65 x VCC 0.8 0.7 0.35 x VCC 0.35 x VCC 0.05 x VCC V V Min Max Units
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74VCX32374
DC Electrical Characteristics
Symbol VOL Parameter LOW Level Output Voltage
(Continued)
VCC (V) 2.7 - 3.6 2.7 3.0 3.0 2.7 - 2.7 2.3 2.3 1.65 - 2.3 1.65 1.4 - 1.6 1.4 1.2 1.2 - 3.6 1.2 - 3.6 0 1.2 - 3.6 1.2 - 3.6 2.7 - 3.6
Conditions IOL = 100 A IOL = 12 mA IOL = 18 mA IOL = 24 mA IOL = 100 A IOL = 12 mA IOL = 18 mA IOL = 100 A IOL = 6 mA IOL = 100 A IOL = 2 mA IOL = 100 A
Min
Max 0.2 0.4 0.4 0.55 0.2 0.4 0.6 0.2 0.3 0.2 0.35 0.05 5.0 10 10 40 40 750
Units
V
II IOZ IOFF ICC ICC
Input Leakage Current 3-STATE Output Leakage Power-OFF Leakage Current Quiescent Supply Current Increase in ICC per Input
0 VI 3.6V 0 VO 3.6V VI = V IH or VIL 0 (VI, VO) 3.6V VI = V CC or GND VCC (VI, VO) 3.6V (Note 7) VIH = VCC -0.6V
A A A A A A
Note 7: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
Symbol fMAX Parameter Maximum Clock Frequency Setup Time
(Note 8)
Conditions VCC (V) 3.3 0.3 2.5 0.2 1.8 0.15 TA = -40C to +85C Min 250 200 100 80 40 0.8 1.0 1.5 1.0 1.5 0.8 1.0 1.5 1.0 1.5 0.8 1.0 1.5 1.0 1.5 1.5 1.5 2.5 3 6 ns Figures 6, 7 Figures 1, 6 3.0 3.9 7.8 15.6 39 3.5 4.6 9.2 18.4 46 3.5 3.8 6.8 13.6 34 ns Figures 7, 9, 10 Figures 1, 3, 4 ns Figures 7, 9, 10 Figures 1, 3, 4 ns Figures 7, 8 Figures 1, 2 MHz Max Units Figure Number
CL = 30 pF, RL = 500
CL = 15 pF, RL = 2k tPHL, tPLH CL = 15 pF, RL = 2k tPZL, tPZH CL = 15 pF, RL = 2k tPLZ, tPHZ CL = 15 pF, RL = 2k tS Setup Time CL = 30 pF, RL = 500 Output Disable Time CL = 30 pF, RL = 500 Output Enable Time CL = 30 pF, RL = 500 Propagation Delay CL = 30 pF, RL = 500
1.5 0.1 1.2 3.3 0.3 2.5 0.2 1.8 0.15 1.5 0.1 1.2 3.3 0.3 2.5 0.2 1.8 0.15 1.5 0.1 1.2 3.3 0.3 2.5 0.2 1.8 0.15 1.5 0.1 1.2 3.3 0.3 2.5 0.2 1.8 0.15
CL = 15 pF, RL = 500
1.5 0.1 1.2
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74VCX32374
AC Electrical Characteristics
Symbol tH Hold Time Parameter
(Continued)
VCC (V) 3.3 0.3 2.5 0.2 1.8 0.15 TA = -40C to +85C Min 1.0 1.0 1.0 2.0 6 1.5 1.5 4.0 4.0 8 ns Figures 5, 7 Figures 1, 5 ns Figures 6, 7 Figures 1, 6 Max
Conditions CL = 30 pF, RL = 500
Units
Figure Number
CL = 15 pF, RL = 500 tW Pulse Width CL = 30 pF, RL = 500
1.5 0.1 1.2 3.3 0.3 2.5 0.2 1.8 0.15
CL = 15 pF, RL = 500
Note 8: For CL = 50PF, add approximately 300 ps to the AC maximum specification.
1.5 0.1 1.2
Dynamic Switching Characteristics
Symbol VOLP Parameter Quiet Output Dynamic Peak VOL Conditions CL = 30 pF, VIH = VCC, VIL = 0V V CC (V) 1.8 2.5 3.3 VOLV Quiet Output Dynamic Valley VOL CL = 30 pF, VIH = VCC, VIL = 0V 1.8 2.5 3.3 VOHV Quiet Output Dynamic Valley VOH CL = 30 pF, VIH = VCC, VIL = 0V 1.8 2.5 3.3 TA = +25C Typical 0.25 0.6 0.8 -0.25 -0.6 -0.8 1.5 1.9 2.2 V V V Units
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VCC = 1.8V, 2.5V or 3.3V, VI = 0V or VCC VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V TA = +25C Typical 6 7 20 pF pF pF Units
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74VCX32374
AC Loading and Waveforms (VCC 3.3V 0.3V to 1.8V 0.15V)
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
SWITCH Open 6V at VCC = 3.3V 0.3V; VCC x 2V at VCC = 2.5V 0.2V; 1.8V 0.15V GND FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and trec Waveforms Symbol Vmi Vmo VX VY
FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic VCC
3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V
2.5V 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V
1.8V 0.15V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V
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74VCX32374
AC Loading and Waveforms (VCC 1.5V 0.1V to 1.2V)
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
SWITCH Open VCC x 2V at VCC = 1.5V 0.1V GND
FIGURE 7. AC Test Circuit
FIGURE 8. Waveform for Inverting and Non-Inverting Functions
FIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 10. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic Symbol Vmi Vmo VX VY VCC 1.5V 0.1V VCC/2 VCC/2 VOL + 0.1V VOH - 0.1V
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74VCX32374 Low Voltage 32-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA96A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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